Probing high-speed digital designs

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The principle applies, but reversed, for V, H max. When transmitting a low level, the output is guaranteed to fall between V 0L min and V 0L max. There is no overlap between the guaranteed output range and the indeterminate input range. The absence of overlap means that static transmitted values, whether 0 or 1, will always be properly received. Actual transmitted values for a particular gate are a function of the ambient temper- ature, the power supply, and the manufacturing process variables used to make that gate.

Typical output levels are marked in Figure 2. The term voltage margin refers to the difference between V 0H and V! Just as logic outputs often exceed the worst-case specification, logic inputs are often more precisely discriminating than the worst-case switching thresholds.

A typical 10KH inverter switching function is shown in Figure 2. As you can see, the circuit exhibits a gain of -4 in the switching region, saturating outside the required switching l2 This means that the transmitted logic 0 voltage will be lower more negative than V ol and the transmit- ted logic 1 voltage will be higher more positive than V OH. Just because this one gate switch- es well within the worst-case switching zone does not mean that every gate will act the same way. The next gate off the assembly line might have a different input DC offset and therefore switch close to one side or the other of the worst-case range.

Military manufac- turers screen parts at the factory to ensure that none ship with switching thresholds out- side the acceptable range. Commercial manufacturers only statistically spot-check these parameters and hope for the best. Why do we need margins? Margins compensate for imperfect transmission and reception of digital signals in real systems.

Systems without adequate margins will not work in the presence of signal corruption such as 1 DC power supply currents, flowing through the DC resistance of the ground path, cause ground voltage differentials between logic devices. A signal transmitted from one gate at a fixed potential above local ground will be received at a different potential if the ground reference between the transmitting and receiving gates is shifted.

These differentials affect the voltage potential of received signals just like DC ground differentials. This is a form of inductive crosstalk. The crosstalk adds to the intended received signal, potentially moving a good signal closer to the switching threshold. Sig- nal transitions may appear smaller or larger at the receiver than at the transmitter.

Margins allow some tolerance for signal distortion. A cold gate transmitting to a hot gate or vice versa may suffer reduced or negative margins. Items 1 and 5 apply to all systems regardless of operating speed and must always be taken into account. Items 2 through 4 are peculiar to high-speed sys- tems. All three high-speed effects vary with the size of the transmitted signal: More return current induces higher ground differentials, more signal voltage or current induces more crosstalk, and larger transmitted signals exhibit more ringing and reflec- tions.

These proportional relations lead us to conclude that an important measure of toler- ance to effects 2 through 4 in high-speed systems is the ratio of voltage margin to output voltage swing. ECL system designers must ensure that the entire system is at a uniform temperature, or else derate the switching margins to account for the difference. Of course, the 10KH family switches two to three times faster than the 74 AS fami- ly.

Faster switching time increases return-current problems, crosstalk, and ringing. Over- all it is more difficult to control return current, crosstalk, and ringing with the MC10KH family than with the 74 AS, but not two to three times harder. A complete voltage margin budget in a system accounts for the effects of power supply variations, ground shifts, signal crosstalk, ring- ing, and thermal differences.

The number of logic packaging schemes is enormous and growing daily. Almost all packages, when used at high speeds, suffer from problems with lead inductance, lead capacitance, and heat dissipation. This phenomenon causes glitches in the logic inputs whenever the device outputs switch from one state to another. The magnitude of these glitches, and the effects they cause, are the subject of this section. One transmit circuit and one receive circuit are shown. The transmit circuit shown is a totem-pole output stage, although any configuration exhibits the same prob- lem at high speeds.

The ground bounce voltage V GND is usually small compared to the full-swing output voltage. It does not act to significantly impair the transmitted signal, but it interferes in a major way with reception. This receiver differentially compares the input voltage V in against its local internal ground reference. This differencing opera- tion appears in Figure 2. In other words, the V CND pulse looks to the inputs circuit like noise directly superimposed on the input signal. If we simultaneously switch N outputs from a chip into N corresponding capacitive loads, we get N times as much ground current and the pulse V GND looms N times larger.

Ground bounce voltages are proportional to the rate of change in current through the ground pin.

How Probes Work

When driving capacitive loads, we expect the rate of change in current to look like the second derivative of the voltage. Referring to Figure 2. Imagine a TTL octal D flip-flop, with a single clock input, driving a bank of 32 memory chips. At 5 pF per input, each address line is loaded with pF. Suppose data comes into the D input with plenty of setup time but with little hold time. Assume this timing meets the requirements of our octal TTL flip-flop. On clock edge A the flip-flop latches in data word FT hex. At clock edge B the flip- flop latches in data 00 hex.

In both cases, the flip-flop propagation delay of 3 ns is slight- ly longer than the required hold time. At point C, let the input data change to any pattern XX. Point C follows 1 ns after clock pulse B. At this point, the flip-flop has internally latched in the 00 data word, but the Q outputs have not yet switched from FF to The next to the bottom trace shows V GND. After point A, when the Q outputs switch positive, the load-charging current flows in the V cc pin, not the ground pin, so we get lit- tle noise on V CND.

This noise pulse causes an error called double-clocking. Double-clocking results from differential input action in the clock circuit. Internal to the flip-flop, the clock input measures the difference between the chip s clock pin and its ground pin. The bottom trace of Figure 2. The difference l4 This is representative of TTL circuits. CMOS circuits tend to compare inputs against a weighted aver- age of V cc and ground. The flip-flop will reclock itself on this pulse.

If the data input has changed by the time the second clock at D happens, the flip- flop will proceed ignorantly to state XX. The Q outputs at point D momentarily flip to the correct state and then mysteriously flip to some wrong condition. External observations of the clock input show a perfectly clean signal; it is only internal to the logic package that anything is amiss. Surface-mounted packages, with their shorter pins, are less susceptible to double-clocking.

As new generations of flip- flops get faster, we will need new packages with less and less ground inductance to house them. Providing special power pins for the output drivers separate from those used for referencing input signals elegantly circumvents the ground bounce problem. Since little current flows in the input ground reference pins, no ground bounce effect occurs.

Most ECL families, and many gate arrays, use separate power pins for this purpose. Edge-sensitive input lines such as resets and interrupt service lines are particularly susceptible to ground bounce glitches. We have the ability to switch pF loads onto any of the three active outputs. This experimental arrangement can show ground bounce with no load or with heavy loads.

Because the inactive fourth output stays at logic LO, it serves as a window into the chip through which we may measure the internal ground voltage. The clock and asynchronous reset lines alternate- ly set and reset the three active outputs. For this experiment we use a 74HC flip-flop. With all three loads connected we get the waveforms in Figure 2.

This corresponds to switching currents internal to the device see Section 2. When the Q outputs switch LO, the big ground bounce pulse appears. In this example it is about mV tall. A pulse of only mV may not seem like much, but consider these facts: 1 The low-side voltage margin on HCT logic is only mV.

Identical measurements carried out on a 74F flip-flop result in a ground bounce of mV. For a resistive load R, we can use Equation 2. Here are typical figures. Table 2. Larger packages have more lead inductance. Packages with internal ground planes do better but do not eliminate the ground bounce problem. Wide, low-inductance internal ground plane struc- tures still have skinny leads connecting the internal ground plane to external ground.

The most promising techniques for dramatically reducing lead inductance are wire bond, tape automated bonding TAB , and flip-chip. All three techniques shorten the ground wire connections between the chip and its printed circuit board. See Figure 2. For an excellent overview of modern packaging techniques, see footnote. The chip and its wire bonds are then sealed with a blob of coating material or covered with a hermetically sealed lid over the entire circuit board.

Wire bonding is a mechanically simple method with plenty of tolerance for changes in either the chip bonding pad locations or printed circuit board wiring. Wire bonding can be done by hand for very low- volume applications.

Design In Probing On High-Speed Buses To Improve Debugging | Electronic Design

Tape automated bonding replaces the wire bonds with a mass termination tech- nique. Interconnecting wiring used to connect the chip to a printed circuit board is first printed on a very thin flexible substrate a flex circuit. This substrate may have more than one layer, including a ground layer for impedance control. Solder bumps are then placed on the chip bonding pads, and the chip reflow-soldered to the flex circuit. The chip now has the flex circuit bonded to its face.

As a second step, the combination chip and flex circuit is reflow-soldered to the printed circuit board. The result is then sealed with a blob of coating material or covered with a hermetically sealed lid over the entire circuit board. For more information contact KBK, Inc. In this method the PCB traces extend under the chip Figure 2. Tape automated bonding, being a mass attachment technique, is very quick.


  • How to Build Your Own Oscilloscope Probes;
  • Probing Pointers, or, Surprising Truths about Scope Probes.
  • parabolic dish solar concentrator.

It has the advantages of providing a continuous ground plane for all signals and also providing some mechanical compliance between the chip and printed circuit board. TAB can accommodate lead spacings as small as 0. The disadvantages of TAB are that a different flex circuit is needed for each chip and that the flex circuit must change if either the printed circuit board or chip bonding patterns change.

Flip-chip technology first places solder balls on each chip attachment pad. The chip is then turned face down onto the printed circuit board and directly reflow-soldered in place. Flip-chip mounting is often used on ceramic multichip modules which incor- 74 High-Speed Properties of Logic Gates Chap. The bonding lengths are miniscule, and so all parasitics associated with packaging are minimized. Mechanically and thermally, flip-chip technology is miserable. There is no mechanical compliance between chip and printed circuit board except the limited springiness of the solder balls themselves.

The thermal coefficient of expansion between the chip and printed circuit board must match extremely closely. In both the wire bond and TAB methods the chip mounts with its back side touching often glued to the printed circuit board which provides a good conduit for heat dissipation. Reprinted by permission of Addison- Wesley Publish- ing Co. Some manufacturers put multiple ground wires on their packages. This is a also good idea if the grounds are spaced evenly around the die. If the grounds are all near eac other going from one to two grounds nearly halves the ground inductance, but increasing the number of nearby grounds beyond two has a diminishing effect.

Spreading the grounds out evenly around the chip is much better than lumping them together. Components which bring out a separate ground reference pin for the input circuitry attack the problem in a more subtle way. These circuits, like the 10K family, provide a separate sense wire for the internal reference voltage generator which has a direct path to the external ground.

This pin does not carry large ground currents and subsequently acquires no ground bounce. This is an excellent method of attacking ground bounce prob- lems. For chips with separated grounds, make sure each ground wire has a direct path to the ground plane. Connecting the two grounds together and then running them through a trace to ground defeats the purpose of having independent ground leads.

Differential inputs are a similar and even more effective means of achieving the same end. We may compute the percentage crosstalk introduced in circuit 2 by circuit 1 using Equation 1. The capacitive crosstalk problem becomes more serious as rise times get shorter.

It also grows worse with higher impedance input connections. Using Equation 2. This means practically all the clock sig- nal from pin 1 will appear on pin 2. Capacitors Q and C 2 reduce the impedance of the receiving circuit at high frequen- cies, heading off capacitive crosstalk problems. When dealing with capacitive loads on a receiving circuit, the percentage of crosstalk is just equal to the ratio of the capacitances: 76 High-Speed Properties of Logic Gates Chap. Checking the lime response of R,C, we get a time constant of 0. No operating the switch will know the difference.

Rig up a p. Also wire up a temperature sen- l7 SUce the package in half, dig on, the interna, circuitry to make room for your resistor and temperature sensor, and glue the thing back together. By varying the volt- age across pins 7 and 14, we can control the power dissipation internal to the package. Next make a plot of internal temperature versus power dissipation. Allow the circuit time to come to thermal equilibrium between each reading.

This linear relation between temperature and power is typical of all logic device packages. The slope of the temperature curves are the same in all cases — we have just Figure 2. From these observations we may synthesize a general formula for predicting the internal temperature of a logic device. The internal temperature called the junction temperature is equal to the ambient temperature plus an offset proportional to the internal power dissipation P. Sometimes a manufacturer will separate the thermal resistance into component pieces relating to the internal workings of the package and its method of mounting.

The most common partition accounts separately for the temperature rise from junction to case and from the package case to the outside ambient environment. Manufacturers of add-on heat sinks pro- vide detailed literature and technical reports on improvements in Q CA achievable with their products. To predict the maximum internal junction temperature when using a spe- cial heat sink, we must find 0 yc from the manufacturer of the device package, 0 CA from the heat sink manufacturer, and the total device power dissipation by our own calculation.

This makes sense because a larger package has a greater surface area and conducts heat more effectively to its surface. Note that for the larger packages, we specify the die size. These are about the largest dies that will fit in each listed package. Smaller dies in the same package have greater thermal resistances, as they have a smaller area of surface contact between die and package. Air speed assumptions are listed along with the entry for each package type. Most heat sinks show a similar increase in efficiency versus air flow velocity.

Data courtesy of Motorola Inc. Scatter plot courtesy of Thermalloy, Inc. Increased air flow lowers the thermal resistance, but not as much as using a bigger heat sink. On land, this is a gentle breeze, but in the restricted air space inside a computer chassis it takes a sizeable fan to move this much air. A large fan is required because as air spreads out from the fan, it slows down. Also, air flow in confined spaces develops turbulent whirlpools and dead zones.

We must blow extra air into a cavity to ensure that at every point inside we attain some minimum acceptable air speed. Output switching currents flowing through a ground pin cause ground bounce, which can cause double-clocking of flip-flops. Thermal resistance is the ratio of temperature rise to power dissi- pation.

When using an oscilloscope to probe inside a digital machine, as with any instrument, we must learn to live with its limitations and to account for them in our analysis of the results. For all but the most sensitive digital work, we are well above the minimum sensi- tivity level of any reasonable oscilloscope. On the high side, digital signals being less than 5 V, 1 we are well within the maximum voltage range of most oscilloscope inputs.

The most serious remaining limitation is bandwidth. Your oscilloscope vertical amplifier undoubtedly has a bandwidth rating, as does your oscilloscope probe. What do these numbers mean? What precisely does bandwidth mean, and how does it affect digital signals? Figure 3. The two traces in Figure 3. The top trace rises quickly, while the bottom trace rises much more slowly. The top trace was recorded with a very fast rise-time probe, and the other with a probe having a limited bandwidth of 6- MHz. The 6-MHz probe, originally manufactured as a noise-filtering, very-high-imped- ance input probe, exaggerates the differences you will see among practical digital probes.

The lower bandwidth probe slurs out and slows down both rising and falling edges of digital signals. In signal processing terminology, the lower bandwidth probe filters out high-frequency components of the signal under test. In Figure 3. Both the probe and the vertical amplifier do the same thing: They degrade the rise time of their input signals. When a realistic input feeds the combination of probe and vertical amplifier, as in Figure 3.

Oscilloscope manufacturers commonly quote the 3-dB bandwidth, F 3dB , of probes and vertical amplifiers instead of rise time. These approximations assume 2 Equation 3 I holds strictly true only when each impulse response in Figure 3. See Append, x B tor more information about the exact calculation of rise time in cascaded systems.

These filters do not have gaussian frequency response curves. Both specifi- cations are 3-dB bandwidths. How will this combination affect signals having 2-ns rise times? Invert the rise-time formula Equation 3. Please do not take this example too seriously. A better approach to finding the rise time would be to use a faster probe or a faster scope.

Manufacturers report probe performance as measured using a test jig connected directly to the probe tip and outer probe shield. No ground wire is used for the probe bandwidth measurement. Since digital engineers commonly use probes with a plastic clip covering the probe tip, and a ground wire connected to the middle of the probe barrel, we should investigate how these modifications affect probe performance. The probe tip connects to the circuit under test, and the ground lead connects the probe barrel to a convenient local ground ref- erence point.

Note that the ground connection is made using a thin wire several inches in length. Examine the equivalent circuit for this probe arrangement, drawn at the bottom ot Figure 3. Here we assume the probe has an input impedance of 10 pF shunted by 10 MQ. The self-inductance of the ground loop, represented in our schematic by series inductance L , impedes these currents. How does the inductance L, affect our measurements? Note that in Example 3. Here we see that the 3-in. This resistor models the output impedance of whatever gate is driving the signal under test.

The Q, or resonance, of this LC circuit is seriously affected by the source resistance of the signal under test. A high-0 circuit rings for a long period after excitation from an outside source. This resonance shows up as a large peak in the frequency response of the circuit. In the circuit in Figure 3. The frequency response plots in Figure 3. A source resistance gives a dB resonance. Digital signals having cutoff fre- quencies higher than MHz will be very much distorted by this probe circuit.

Digital signals having cutoff frequencies higher than MHz will be distorted by this probe circuit. Source resistances near 12 yield the best frequency response with this probe. Digital signals having knee frequencies lower than MHz exhibit no artificial ringing or overshoot when displayed with the probe illustrated in Figure 3. Probe input impedance is 10 pF, 10 M n Figure 3. The 5-ns rise-time limit is a function of this particular probe arrangement having nH of loop inductance and a pF shunt capacitance.

Figures 3. These experi- ments were conducted using a very-low-capacitance FET input probe, rated at 1. The top trace in each photo is recorded using a standard plastic probe clip covering the probe tip, and a 3-in. The middle trace is recorded with the bare probe tip touching the signal under investigation, and a 3-in. Evidently, taking off the plastic probe clip has little effect. The ringing periods evident in the figures are in the range ns.

What about the bot- tom trace in each figure? Why is it better? The bottom trace in each figure gives us a good hint as to how to solve the over- shoot problem. In the bottom trace, we have removed the plastic barrel which holds together the ground wire assembly and removed the ground wire, exposing the metal shield which covers the probe all the way out to the bare probe tip. Then, using a small knife blade, we connect the metal probe shield directly to the circuit ground as near the signal sense point as possible see Figure 3.

This shorts the metal probe shield to ground with as little inductance as practical. Why does grounding the probe close to the signal source help? The basic reason is that we have radically reduced the ground loop inductance of the probe assembly. Reduc- ing the inductance reduces the probe rise time Equations 3. How small must we make the probe ground wire inductance to guarantee a low q and a fast rise time? Is it possible to just use a shorter ground wire instead of both- Sec.

Table 3. TABLE 3. For ECL circuits, we would need even lower inductance. Reworking Equation 3. The slow variation in 92 Measurement Techniques Chap. To make a big difference in inductance a factor of 10 we must increase the wire diameter until the two sides of the loop almost come in contact with each other. Wire stiffness, on the other hand, is proportional to the cube of wire diameter and so goes up markedly with increases in diameter.

The stiffness and inductance factors work against each other. There is no reasonable way to cure the probe inductance prob- lem by just using a bigger wire. Inductance is roughly proportional to loop area and to wire length. Common fixes for inductance problems involve shortening wires or reducing loop sizes rather than increasing wire diameter.

In addition, the response will ring when driven from a low-impedance source. Fattening the ground wire hardly helps with ringing. Radically shortening the ground loop improves ringing and reduces rise time. Additive noise coupled through the probe ground loop masquerades as noise that is naturally present at the signal node under test.

This additive noise, if synchronous with the signal under test, is difficult to separate from real features of the signal. The signal current loop is shown in heavy black lines. The changing current in loop A, acting through the mutual inductance of loops A and B, induces voltages in loop B. We will first estimate the changing currents in loop A and then calculate the mutual inductance of A and B. Finally, we will use the definition of mutual inductance to find the noise voltage received by an oscilloscope under these conditions.

The maximum dlldt is 7. By itself 12 mV may be safely ignored. What happens, though, if the probe ground loop moves near a bit bus? It is highly likely that the noise voltages from each bus line will add resulting in a nettlesome disturbance of 0. This disturbance is comparable to the total voltage margin in TTL systems and represents a serious source of measurement error.

Faster logic compounds the noise-pickup problem. Ideally, you should see no signal at a. On the contrary, anyone who has done this experiment knows that near fast digital logic, you see plenty. As the loop moves near high-speed digital cir- cuits, it picks up noise coupled through mutual inductance. This same noise adds to any measurement made using a similar-sized ground loop. If you crush the ground wire tightly against the body of the scope probe, the loop area decreases and you will see less coupling.

The amount of noise coupling is directly proportional to the ground loop area. The exposed probe tip area is usually so small that significant mutual capacitances do not exist between it and digital circuitry. Try holding the probe near a high-speed digi- tal circuit, with no ground wire at all, to see if mutual capacitance between the circuit and the probe tip induces measurable noise current in the probe.

Probes are very well electro- statically shielded. Keep the probe ground wire as short as possible or use a knife blade to short the probe shield directly to the circuit board ground. Make a magnetic field detector to test for noise induced by mutual inductive coupling. Surely, we have all encountered circuits that work when we are probing them but malfunction as soon as we withdraw the probe.

This is a common occurrence, due simply to the loading effect ot the probe upon the circuit in question. When a probe loads down a circuit, what changes in waveform do we expect. Believing for the moment that typical digital source impedances range from 10 to 75 O, we need only study the behavior of scope probes versus frequency. Referring to Figure 3. At high frequencies, only the shunt capacitance matters.

Otherwise, there are resonances. For any rise time less than 5 ns, the pF probe fails to pass muster. At the terminating location connect a sensing probe consisting of a Q resistor feeding a short length of RG ft coax. The other end of the sense coax leads to a 50 -Q terminated input on a high-speed sampling scope. We may now connect various loading probes to the test point, and watch their effects.

The first trace was recorded with no loading probe connected, the second with the loading probe connected using a 6-in. The first trace has the best rise time of ps, with a moderate amount of ringing. The second trace, while exhibiting little rise-time degradation, has a bigger undershoot ripple following the initial rising edge.

The first trace ripples also but stays within half a division of the asymptote. The final trace displays a rise time of ps, with very little ripple. When connected, as in the third trace, with little series inductance, the probe behaves as a simple capacitive load. The source impedance of the test point in Figure 3. Then load the test point with a probe and observe the difference. That s as accurate as we can expect to get. While the probe loading increased the rise time by ps, it increased the delay by only ps. Less probe capacitance means less circuit loading and better mea- surements.

With this type of probe, there is not much hope of accurately viewing, say, 2-ns rising edges. Compounding this problem, the probe itself will significantly alter the signal rise time and pulse shape when attached to a circuit. This section presents three measurement techniques that directly attack the prob- lems of ground loop inductance and shunt capacitance.

This probe is made from ordinary Q coaxial cable RG, RG, or RG-8 soldered to both the signal under test and the local circuit ground at the point of usage. The probe terminates at the scope into a Q input jack. The total input impedance of this probe is therefore Q. This is very favorable. Assuming a Q BNC input jack is used on your oscilloscope, the BNC connector introduces a series inductance in the Q cable at the point where the shield spreads out away from the center conductor to connect with the BNC fitting.

Get a good-quality in-line terminator for this setup. The cable rise time is proportional to the square of the distance. There is a fixed constant of proportionality between the results for each cable type. You can approximate the rise time of a coaxial cable by first finding the frequency at which the attenuation equals 3. This value, for coaxial cable, is the knee fre- quency. This formula works only for short lengths of cable total attenuation less than a few decibels. Note that the attenuation at high speeds is proportional to the square root of fre- quency.

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Attenuation is directly proportional to length. Keep this path very tight for good results. As a function of sense loop diameter. Because the shop-built probe incorporates a 1K-L2 input resistor, the rise-time degradation, UR, due to the inductance of the sense loop is much smaller than when working with a Q coax or with a pF input probe.

The shop-built probe has a terrific rise time. With bigger resistors, the rise time gets even better. One factor limiting the use of attenuating probes is the end-to-end shunt capaci- tance of the attenuating resistor.

At very high frequencies the shunt capacitance feeds additional unwanted power into the coax, further loading the circuit under test. Another way to combat shunt capacitance is to intentionally place a capacitor in shunt with the sensing end of the coax. The correct-value capacitor, working with the shunt capacitance of the sense resistor, forms a matched divider network.

This net- work has a flat frequency response up to exceptionally high frequencies. Commercial oscilloscope probes use this technique. Attenuating probes have a low Q. You will experience few overshoot and ringing problems with a properly made probe. Tektronix manufactures a variety of low-impedance, passive attenuating probes built basically like the shop-built model. This product line includes the P, P, and P The P may be used with any vertical amplifier provided it has a B input and Q internal termination.

From Table 3. Remove the plastic clip, revealing the probe barrel. If necessary, then disassemble the apparatus holding the ground wire in place, exposing the low-inductance probe ground sheath. This metal sheath, or ground collar, extends out almost to the end of the probe tip. It serves two purposes: electrostatically shielding the probe tip and providing a good ground point near the tip for implementing a low-inductance sensing loop. Buy with Assurance. P Data Sheet. Continue Shopping. Calibrate and Repair. Sell To Us. Why MATsolutions?

Customer Feedback. The inductance of a pair of needle-nosed pliers used to short the same nodes one plier tip on each node is on the order of nH. The trip up one leg of the pliers, through the joint, and back down the other side introduces an order of magnitude more inductance than a small knife blade. Thirty ohms is not low enough to ground out a short TTL pulse. Enough said. The measured output waveform is not a clean exponential shape but is more complex. Careful observation of the peak amplitude in Figure 1. This evidence suggests that the exponential time constant measured in Example 1.

Were we to go further out on the waveform to measure the decay constant, away from the initial step, the actual wave would decay more exponentially. We would like something that considers the whole waveform, not just the Sec. Our next approach uses the measure of total area under the curve in Figure 1.

The total com- puted area is In the absence of automatic assistance, a simple trapezoidal approximation based on seven points is an effective way to measure area by hand. Posi- tion points at the beginning, halfway up the rising edge, and at the top. Then sprinkie the rest along the decay curve. We now show the simple mathematical relation between the area under the curve and the inductance L.

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An Introduction to Oscilloscope Probes

Noise immunity accrues because noise tends to average to zero area. Immunity to waveform distortion due to the limited rise time of the observing equipment is a more interesting property. Any perturbations in the frequency response of the scope or signal generator not affecting the DC response will also not affect the area under the response curve. One may resort to Fourier integrals or to the definition of signal convolution to prove these remarks.

A slow pulse generator rise time, or a slow scope, does not change the area measured with our inductance test jig. Voltages in one circuit cre- ate electric fields, and these electric fields affect the second circuit. Every two circuits interact electrically, with the coefficient of interaction decaying rapidly with increasing distance. A mutual capacitive coupling between two circuits is simply a parasitic capacitor connected from circuit A to circuit B. A complete formula would use the difference in voltages between circuits A and B and the loading effect of capacitor Of on both circuits.

The simple approximation Equation 1. We can ignore the small coupled voltage on B when calculating the noise current and assume the voltage difference between circuits A and B simply equals V A. We will calculate the coupled noise voltage as l M times the impedance of circuit B to ground. This procedure ignores interactions between the mutual capaci- tance and the secondary circuit.

The PCB has a solid ground plane on the solder side only and is blank on the circuit side. The resistors seat firmly against the circuit side of the PCB, 0. The back termination on the pulse generator is engaged as is the scope terminator. No copper on circuit side of printed circuit board PCB 0. The driving waveform has a rise time of about ps.

We can estimate the mutual capacitance using an area formula similar to Equation 1. B , that equals the step change in voltage times the mutual capacitance. If we ground one end of each resistor in Example 1. A divides the driving voltage in half. The ground on one side of resistor R B allows the coupled current to split, with two-thirds of the current flowing via one side of resistor R B directly to ground, and one-third of the current flowing the other way. The other path leads through the opposite half of resistor R B , through the coax cable to the scope, and on to ground.

The product of one- half the drive voltage and one-third the receive sensitivity is one-sixth. When we use resistors in the configuration in Figure 1. We will see in the next section that mutual inductive coupling is more of a problem than mutual capacitance in digital designs. The current in one loop creates a magnetic field, and that magnetic field affects the second loop. Every two loops interact, with the coefficient of interaction decaying rapidly with increasing dis- tance. A mutual inductive coupling between two circuits acts the same as a tiny transformer connected between circuit A and circuit B as shown in Figure 1.

Anywhere we see two nearby loops of current, the two currents interact like the primary and secondary of a transformer, and we get mutual inductance. Equation 1. A complete formula would use the difference in currents between primary and secondary and the loading effect of the primary and secondary windings on both circuits.

The assumptions surrounding the use of Equation 1. Attaching L M therefore does not load circuit A. Noise voltages coupled by mutual inductance in digital products are always smaller than the source signal. Source of changing Figure 1. Just add the coupled noise voltage to the voltage otherwise present in cir- cuit B. This procedure ignores interactions between the mutual inductance and the secondary circuit. In digital circuits mutual inductance, like mutual capacitance, usually induces unwanted crosstalk between circuits.

At stronger cur- rents, more magnetic energy is stored per unit volume in the space surrounding loop A. The total magnetic field strength over the area of loop B, called the magnetic flux in B, is a function of the distance between loops A and B, their physical proportions, and their relative orientations and is di- rectly proportional to the current in A. More current in A produces more flux in loop B.

Linking together ideas 1 through 4 , we see that the voltage induced in loop B is proportional to the rate of change of current in loop A. The constant of proportionality is called the mutual inductance between circuits A and B. Because a magnetic field is a vector quantity, flipping over loop B has the effect of reversing the polarity of flux coupling. The coupled noise voltage reverses polarity.

Flip- ping over loop A has the same effect. Orienting loop B parallel to the local lines of mag- netic field strength results in zero net flux passing through B and zero noise coupling. Mutual inductive coupling, unlike mutual capacitive coupling, is capable of inducing crosstalk with a polarity opposite that of the driving signal. It is also highly sensitive to loop orientation. This situation commonly arises when we drive a voltage V t through a transmission line terminated resistively.

Two carbon-composition resistor bodies are mounted as in Example 1. The right-hand ends of both resistors are grounded, and the measuring cables, IN and OUT, connect to the left end of each resistor, respectively. Resistor R A serves as a termi- nation for the signal source. The signal source has a rise time of ps. This right-angle connection separates the cables as much as possible, reducing the direct feed-through. The back termination on the pulse generator is engaged. The proportion of the total flux from R a that encircles resistor R B is a constant determined solely by the physical dimensions and positions of the two resistor bodies.

Magnetic field lines that encircle resistor R B are said to penetrate the loop formed by resistor R B. B , imagine a current loop starting at the grounded end of R B. From there, travel through R B into the coaxial probe, down the coax to the internal terminating resistor R T in the scope, through that resistor back to the scope chassis, back down the coax shield to the local ground plane, and across that local ground plane back to R B. Any change in the total magnetic flux passing through this loop induces a voltage around the loop. With equal-value resistors at positions R B and R Jy the induced voltage divides equally between them, so we expect only half the total induced voltage at the scope.

If resistor R B were a 0-Cl resistor of the same physical dimensions, we would see the full induced potential at the scope. From the measured result in Figure 1. The mutual capacitive interference area, from Example 1. Then connect the left side of R B to ground. We have effectively reversed the leads on the transformer-like inductive coupling between R A and R B. This reversed pulse equals one-half of the inductive coupling minus one-sixth of the capacitive coupling from Example 1.

The inductive and capacitive couplings now have reversed signs, and so their effects subtract instead of adding. We must correct the area measurement from Figure 1. In these cases the total inductively coupled signal energy ends up at the far termination rather than being split in two as in Example 1. Every designer wants power low, speed high, and packaging cheap. Unfortu- nately, no logic family satisfies users on all fronts. We are forced to choose from a vari- ety of logic families, each tailored in some way to a particular application.

Will this need for variety ever go away? Will we ever have a perfect logic family suited for all needs? Historically, the answer has been no. Even when a new technology sweeps the field, superior in every way to its competition, users pressing for every advantage in their designs will still demand variety. All logic families exhibit tradeoffs among power, speed, and packaging, and all logic manufacturers do their best to exploit these tradeoffs. The wire spring relay was the last and best gen- eration of relays used for logic machines before electron tubes took over.

The contact elements of the wire spring relay were supported on the ends of long thin wires which themselves formed the spring element of the relay. The small size, low mass, and simple construction of the wire spring relay made it a very fast-acting, cheap alternative to traditional relay designs which incorporated separate assemblies for the spring and the contact armature.

Wire spring technology quickly swept the competition, and crossbar telephone exchanges were manufactured by Western Electric using wire spring relays as late as Wire spring relay technology encompassed more than just relay construction, it affected system packaging as well. The relays plugged into arrays of sockets on standard relay panels and stood shoulder to shoulder, saving space.

Wire wrap pins protruded from the back side of each relay panel for inter- connections. With a standard relay package, manufacturers could use the same relay rack panel for many different applications, according to the pattern of the wire wrap connections on the back side. This compared to the earlier practice of designing individual relay-mount- ing locations for each device, often incorporating peculiar spring latches, actuators, or other mechanical contrivances which tightly coupled relay construction to the overall purpose and function of a digital machine.

Wire spring relay designs separated the electri- cal and mechanical elements of a system. This packaging approach lowered overall design and manufacturing costs. Standard packaging was cheap but sacrificed a lot of flexibility. The standard pack- age held no more than one relay having 12 poles of double-throw contacts 12PDT. Users requiring larger monolithic relay operations had to split them up among multiple packages, dissipating more power with each additional package. Splitting up operations was inefficient. For cost reasons.

Western Electric engineers chose not to incorporate heat sink fins on each package. For reliability, they used simple convection cooling in all their equip- ment. These factors limited the total power dissipation allowed inside each relay package. This power limitation, coupled with the limited space inside the standard package, ulti- mately meant that Western Electric could place no more than two drive coils inside each package.

The most dense wire spring relay configuration was a dual 5PDT relay two independent relays each having five poles of double-throw contacts. The relays operated from a standard V power supply and were available with either or Q coils. Why two coils? The Q coil consumed much more drive current and therefore switched much faster than the Q coil. On the other hand, the Q. Because of their heat advantage, coils could be packed closer together than coils.

Maximum operating speed and maximum logic density were both indirectly determined by power dissipation. Do these issues sound familiar? Are logic systems today still constrained by pack- aging, power dissipation, and speed tradeoffs? Of course. We face today many of the same issues confronted by our predecessors. Power, speed, and packaging are all still heavily interrelated. The modern tradeoffs for high-speed design sound like this: 1 Standard packaging of logic devices saves money in manufacturing but reduces flexibility.

The initial investment required to support a new package type is stagger- ing, and so most system designers stick with whatever packages their device ven- dors offer. Both factors force designers to partition large systems among many device packages. Because signal connections between packages respond more Sec.

The cooling properties of the package are independent of the semiconductor die placed inside the package. Packages with good cooling properties always cost extra. Higher-density packaging has the benefit of cutting assembly cost and product size dramatically but often dissipates more total power per package. The maximum allowable power dissipation per package eventually constrains the num- ber of gates per package. At the highest speeds, maximum power dissipation per package again becomes a limitation. The next section presents the specific relations between power and speed for mod- ern logic families.

Typical power dissipation as rated by the manufacturer often ignores additional power dissipation which occurs at high speeds, plus power dissipated by driving heavy output loads. These effects can often cause the actual power supply cur- rent to sometimes far exceed the typical l cc rating. We will study the power consumption of high-speed logic circuits according to the four power categories illustrated in Figure 2. Each of the four power categories further subdivide into active and quiescent dissipation. It is quiescent power, under no load, that we see most often quoted on data sheets.

In the examples that follow we simply average the power during high and low states when figuring quiescent dissipation. If your circuit spends more time in one state than the other, consider using a weighted-average, or worst-case, figure. At time t j switch A closes, charging the capacitor up to Voc- As the capacitor charges, current surges through the finite charging resistance of the drive circuit. This current surge dissipates energy. At time t 2 switch B closes, discharging the capacitor through the finite discharg- ing resistance of the drive circuit.

This current surge also dissipates energy. In a system with random transitions, F equals one-fourth the clock rate. This arrangement of two active circuits, one that pulls the output voltage HI and another that pulls the output voltage LO, is called a totem-pole output stage. This feature pre- vents heavy currents that might otherwise flow if Q 2 and Q, simultaneously conducted. Every logic family having a totem-pole output contains some circuit feature meant to pre- vent both HI and LO output drivers from conducting simultaneously.

Experimentation with the TTL driver circuit depicted in Figure 2. The stored base charge effect created a fixed period of overlap. New Schottky circuits do not saturate transistor Q 2 and therefore exhibit less overlap current. CMOS circuits, depicted in Figure 2. The exact value of the V GS parameter is highly dependent on the manufacturing process, so it is unwise to generalize knowledge gained from mea- CMOS totem-pole output stage s i Output i Ground Figure 2.

Figure 2. Permission granted by Philips Semiconductors-Signetics. With a fast input transition, the size and shape of the overlap current pulse is con- sistent on every cycle and dissipates a consistent amount of energy per cycle. The extra power dissipation due to overlapping bias currents is therefore proportional to the switch- ing cycle rate. Unlike power dissipation due to load capacitance, the power due to over- lapping drive currents does not grow with the square of power supply voltage. As shown in Figure 2. For TTL circuits, the overlap effect is more pronounced. If you take a TTL inverter and connect its input to its output, it will bias itself into the overlap region and dissipate a lot of power.

You can feel the circuit warm up. TTL circuits are therefore not good candi- dates for use as linear, small signal processing elements like oscillators because they draw excess power in the linear state. Emitter-coupled logic ECL circuits, on the other hand, draw no additional current at the crossover region and make excellent linear pro- cessing elements. It is required to bias and activate the input circuits. In each case, the quiescent input power is determined by multiplying the required input current by the power supply voltage.

This sums the actual power dissipated inside the receiving logic device with power dissipated in the driving device. For active input power calculations, we plug the input capacitance, the typical input voltage swing, and the operating frequency into Equation 2. This computes the total power dissipated in any circuit which drives this input. These input power figures are relatively low. They gain significance only for nets having unusually large fan-out, or for systems which must operate on extremely low power.

TABLE 2. Internal power includes both quiescent and active power dissipation. Quiescent internal power is defined with no loads connected and with the inputs in a random state. Leave the output pins disconnected. Measure the total power P loU , at cycle rate F hertz and calculate the active power dissipation constant.

CMOS devices exhibit a clear linear relationship between internal power dissipa- tion and cycle frequency over a very wide frequency range. That relationship is easy to see because the internal quiescent power drain of CMOS circuits is incredibly low. TTL devices exhibit the same phenomenon, but their large quiescent power drain masks the effect until the cycle frequency approaches the maximum operating frequency of the device.

Above 10 MHz, the active power consumed becomes larger than the quiescent power, and the total power curve looks proportional to frequen- cy. Below 1 MHz, the active power is less than the quiescent power and the total power curve looks flat with respect to frequency. Reprinted by permis- sion of Texas Instruments. Remember that the voltage swing V is squared in Equation 2. Equations 2. Some CMOS devices work over a wide range of operating voltages. The amount of power dissipated in output drive circuitry depends on the output circuit config- uration, the logic levels, the output load, and the speed of operation.

Because the characteristics of each output will be important later in understanding transmission lines, we delve into a lot of detail here. We will compute the power in both LO and HI states and average the two values. The idealized TTL driver illustrated in Figure 2.

The voltage drop ho for standard TTL, is fixed by the satura- tion of Q 2 at about 0. Schottky TTL logic has a slightly higher low-level output voltage under load of about 0. Note that Q x does not go into saturation because its base never rises more positive than its collector. CMOS drivers more closely resemble the circuit in Figure 2. From a CMOS data sheet you can usually get an idea of the values for R A and by examining the output voltage versus output current specifications, as explained in Example 2. This effect shows in the specifications for HC not HCT logic, which runs at power supply voltages anywhere between 2 and 6 V.

Consequently, HC logic runs faster at higher voltages. This is particularly tempting when designing CMOS bus structures, as the theoret- ical fan-out capacity is unlimited. Heavily loaded bus structures suffer two disadvantages: The rise time will be slow, and the driver power dissipation will be high. Example 2. The bus connects 20 small CPUs, any of which may access an 8-bit- wide random-access memory.

The entire system fits on one large circuit card. The bus is implemented using Q controlled-impedance traces that are 10 in. We expect, based on the DC fan-out parameters, that each bus driver should easily be able to drive 20 other circuits. Given the 9-ns maximum propagation delay of each transceiv- er, we plan to operate the bus on a ns cycle 33 MHz. To check out this design, compute the load capacitance on each trace and compare that to the drive resistance of the three-state outputs.

Then figure the RC rise time of the bus. Last, calculate the power dissipation inside each driver. Load capacitance Each driver, when switched to its OFF state, still presents a capacitive load. We 6 HC logic may be powered anywhere from 2 to 6 V. Its switching threshold lies halfway between V cc and ground. Modeling the resistance is a difficult task not generally worth the rewards. Some data books claim their output drivers act like perfect current sources, which is also not true.

Whichever method you follow, corroborate your calculations with a physical measurement. We thought we were using drivers with a 9-ns maximum propagation delay, but the actual delay turns out to be 53 ns! This bus design is impractical both because the rise time is too slow and because the driver power dissipation is too high.

We must derate this bus below 16 MHz. This circuit sources current in both HI and LO states. The logic HI and LO output voltages are similar for both the 10KH and 10G fami- lies, although subtle differences exist in the temperature- tracking characteristics of vari- ous ECL and GaAs emitter-coupled logic families. These families are normally powered by a The output HI voltage most positive is nominally Emitter-coupled logic circuits require a pull-down resistor, usually terminated either to We present here calcula- tions for both cases. When the same circuit is pulled down by resistor R to This happens because when pulled down to only Less current means less power.

Less current also means a slower fall time when the circuit transitions from HI to LO. Because the output circuit is an emitter follower, the rise time is independent of the pull-down current. Appendix B explains more precisely how to combine several independent rise time effects into a com- posite rise or fall time. Only the pull-down resistor discharges capacitor C. This is where the relationship between power and rise time comes into play. The fall time is directly proportional to how fast we pull current out of capacitor C. The power dissipation is proportional to the quies- cent pull-down current.

Whether our pull-down resistor is connected to At point E the voltage has decayed down to Uo and transistor Q x turns back on, arresting further decay. When ECL powered by The Reasonable values for pull-down resistors to -2 0 V in ECL logic range from 50 to Q, corresponding roughly to the range of prac- tical transmission line impedances. Reasonable ranges for terminating resistors to These higher resistances do not work as well as terminators.

With either circuit, reducing the resistor value dissipates more power w i ing the fall time. For the same fall times, both circuits dissipate similar amounts ot power. Dissipation due to the pull-down resistor which is also responsible for ensuring a quick discharge of any load capacitance is usually much larger than the active power required to charge up any load capacitance. The same is true for open collector circuits and for current source output circuits.

Any capacitive loads present cause fall-time problems well before contributing apprecia- bly to drive circuit dissipation. Low- output capacitance is the primary benefit of BTL technology.

Doing more, with less

BTL output Figure 2. Totem-pole output circuits always leave a reversed biased base-to-emitter or dis- abled gate-to-source junction connected to the line when tristated. The capacitance of this junction, which must be physically big to support large output drive currents, is much greater than an ordinary input capacitance. Their current outputs naturally superimpose on each other when driving a long bus, in contrast to voltage source outputs which interact in a nonlinear fashion. Because these circuits are designed as linear class-A amplifiers, the driving transis- tor does not saturate and the output circuit consequently dissipates a lot of power.

Open collector drive circuits either draw a lot of current with little voltage drop or have a big voltage drop with no current. Both states consume little power. Current source drives, on the other hand, sometimes draw a lot of current with a big voltage drop in one or both states. Despite their power inefficiency, current source outputs have big advan- tages in long bus structures.

These clock signals propagate from left to right parallel to the data bus. Each bus driver, named alpha, beta, or gamma, is responsible for inserting data on the bus at predetermined time slots. The timing of bus transmissions coincides with the arrival, at the transmitting device, of a clock signal. This arrangement guarantees that the each data cell arrives at the right-hand end of the bus properly framed within the clock interval, regardless of the physical position on the bus at which it was transmitted.

The one and only receiver is located at the right end of the bus, and it clocks data off the bus synchronously with arriving clock signals. Beta begins sending at time t 2 and stops one clock interval later at time t 6. This time corresponds to the instant when clock signals A and B arrive at position Beta. Alpha starts sending at time t 5 , when clock signals arrive there, and stops one clock interval later. As each device transmits, its signal propagates both to the right and to the left along the data bus.

At the right end of the data bus, both signals end up properly framed in their assigned positions. So far, there is no theoretical limitation to the speed at which we may operate this bus. Because we do not have to wait for the clock to propagate down and back to remote devices, we can raise the clock rate to any arbitrary frequency, limited by the operating speed of the associated devices but not by the physical propagation velocity and length of the bus.

The bus can carry several data cells simultaneously, all propagating to the right toward the receiver. The disadvantage to this one-way arrangement is that while we care only about sig- nals at the right end of the bus, the transmitted signals actually propagate in both directions. Examine what happens at point t 2 when Beta transmits. Its transmitted signal goes to the right where it is received and also backward toward Alpha.

At point t 5 , when Alpha should start transmitting, the tail end of datum A from Beta is passing by on the data bus. If transmitter Alpha is a totem-pole driver, and if the values of datum A and datum B match, no current flows from device Alpha onto the data bus until datum B has completely passed. The data bus is already at the correct logic state, and so transmitter Alpha has no effect. It is as if Alpha were never connected. At the receiving end, because no transmitted wave emanated from Alpha until well into its assigned time slot, the front end of received datum B is missing.

Similarly, if the bit polarities are opposite, Alpha must work twice as hard to drive the bus output, and the front end of datum B, as seen at the D input, will show a larger-than-nor- mal pulse. The solution to this problem is to use a linear mode drive circuit which superimposes its own signal onto whatever happens to be present on the line. The correct circuit configura- tion is a current source, usually implemented as either an open collector or open drain cur- rent regulator circuit.

This circuit injects a predetermined amount of current onto the data bus. The data bus, responding like a resistive load, 9 produces a corresponding shift in volt- age. One of the two logic states is usually defined as zero current, and inactive devices switch to that state. Depending on the length of the bus, each driver might operate in the presence of sev- eral simultaneous datum passing by, each from a different driver located at different posi- tions along the cable. This requirement implies that the driver must supply a linear current over a wide range of voltages.

The combination of constant drive current over a large range of voltages wastes a lot of power. This section computes the power dissipated in the load itself. First, remember that ideal capacitors dissipate no power. Power is dissipated in the driving circuit that charges and discharges the capacitor, but not in the capacitor itself. Dissipation in bias resistors is often high- er than in the driving circuits, so one sometimes worries more about burning resistors than about burning logic gates. The power supply can be sized to handle the expected average dissipation, plus a moderate safety factor.

Power supplies have fuses and thermoelectric cutoff circuits to protect them in case of overload; bias resistors do not. In contrast, practical problems in high-frequency engineering often depend solely on a more subtle specification: the minimum output switching time. Faster switching times cause proportional increases in problems with return currents, crosstalk, and ringing that are independent of propagation delay.

Logic families having minimum switching times much faster than the propagation delay suffer an unnecessary penalty in system design because the device packaging, board layout, and connectors must accommodate fast switching times while the logic timing benefits only from propagation 60 High-Speed Properties of Logic Gates Chap.

Given two logic families with identical maximum propagation delay statistics, the family with the slowest output switching time will be cheaper and easier to use. Many logic families are available at a variety of speed-power combinations. All CMOS families exhibit a dramatic power-versus-speed relationship linking the power dissipation of any CMOS system proportionally to the clock speed.

Manufacturers emphasize the tradeoff of speed and power because it is easy to see on a data sheet. This parameter is difficult to control unless the manufacturer inserts special circuitry to slow down the output switching rate. Circuits that limit switching time have slowly crept into a few logic families. Since that time, other manufacturers have been getting the idea. Excessively fast switching times cause problems through two distinct mechanisms, effects created by sudden changes in voltage and effects created by sudden changes in current. If the frequency response of a pathway is not flat up to F knee , signals received at the far end of the pathway may have impaired rise times, lumps, overshoot, or ringing.

Too short a rise time high dVidt pushes up the value of F knee , making the signal propagation problem that much harder. This crosstalk occurs through the mechanism of mutual capacitance see Section 1. Two cir- cuit elements placed nearby will always interact capacitively. As hinted in Section 1.

#74: Basics of Differential Probes for Oscilloscopes and their applications: a tutorial

This crosstalk occurs through the mechanism of mutual inductance see Section 1. Two circuit ele- ments placed nearby will always interact inductively. To calculate the amount of induc- tive coupling, we must first estimate the rate of change of current in the source network. It makes sense that circuits having a high rate of change in current will have greater prob- lems with inductive coupling. This is the primary disadvantage of too high a dlldt , Since our primary probing instrument, the oscilloscope, reads out voltage, not cur- rent, we need a way to translate from voltage rise-time readings to rates of change in cur- rent.

The maximum value of the rate of change in current will be useful for determining the peak value of inductive coupling. Summing will somewhat Sec. These examples show that ECL systems do not necessarily generate higher cur- rent-switching transients than TTL systems. The ECL system is faster but makes less noise.

These gates have voltage-sensitive inputs whose guaranteed 0 and 1 switching thresholds appear in the figure as V IL min and V IH max, respectively. Received voltages that fall between the two thresholds may be interpreted by the receiving circuit as a 1, as a 0, or as an indetermi- The term V IL min implies that, across all gates, it is the minimum value ot V IL required to guarantee a low input level.

Manufacturers do not state how great the low-side switching threshold might be; they only specify its minimum value. The principle applies, but reversed, for V, H max. When transmitting a low level, the output is guaranteed to fall between V 0L min and V 0L max. There is no overlap between the guaranteed output range and the indeterminate input range. The absence of overlap means that static transmitted values, whether 0 or 1, will always be properly received. Actual transmitted values for a particular gate are a function of the ambient temper- ature, the power supply, and the manufacturing process variables used to make that gate.

Typical output levels are marked in Figure 2. The term voltage margin refers to the difference between V 0H and V! Just as logic outputs often exceed the worst-case specification, logic inputs are often more precisely discriminating than the worst-case switching thresholds. A typical 10KH inverter switching function is shown in Figure 2. As you can see, the circuit exhibits a gain of -4 in the switching region, saturating outside the required switching l2 This means that the transmitted logic 0 voltage will be lower more negative than V ol and the transmit- ted logic 1 voltage will be higher more positive than V OH.